1. Field of the Invention
The invention relates to data transfer control systems for routing data between magnetic tape storage devices and main memory in a data processing system, and more particularly to a logic control system for accommodating a data transfer between magnetic tape storage mediums and data processing units having different data formats, densities and code conventions.
2. Prior Art
In a data processing system wherein a plurality of functional units are electrically coupled by a common communication bus, medium performance device controllers (MPDC) have been employed to accommodate data transfers between mass storage devices and the main memory of the data processing system. In order to relieve the CPU of an unnecessary overhead burden, the MPDC has included a Read Only Store (ROS) memory having microprogram instructions stored therein to provide a near autonomous operation. The MPDC thus is a microprogrammed peripheral control subsystem for storing and retrieving data from main memory, and communicating with mass storage adapters which have the facility to support one or more mass storage devices such as magnetic tapes or disks.
In contemporary data processing centers, it is not uncommon for a single user to require access to more than one data processing system. Where the data processing systems are provided by different vendors, a difference in the data densities, the number of tape tracks, the data packing formats and the processing codes may be encountered. For example, one system may use seven-track tapes having 500 bytes per inch, another system may use nine-track tapes having 6250 bytes per inch. One processor may have six-bit bytes, and another have eight-bit bytes, thereby requiring a packing or depacking of data. Data stored in an IBM memory may be in the IBM EBCDIC code, while that stored in a Burroughs memory may be in a different Burroughs EBCDIC code. Thus, when data is transferred between the two systems, a code conversion is required.
To provide maximum flexibility, the device controller must remain primarily identified with a single data processing system. A single system design thereby may be solidified for marketing. When further flexibility is required, that flexibility is implemented at the adapter level to avoid undue impact on the manufacture of the main system product. This approach is thwarted, however, if the adapter becomes too complex to interface efficiently with the existing controller logic. Packaging constraints thus also enter into play.
In view of the above, it is apparent that an adapter having minimal logic device redundancy, and an architecture designed with a view toward simplicity is required to markedly reduce manufacturing and maintenance costs.
The present invention provides a unique combination of shift registers and FIFO units to effect a 1.times.1, 4.times.3, 8.times.5, 8.times.7 or 8.times.9 packing or depacking of data without substantially complicating the logic system, and provides recursive data paths through the use of tri-state logic to minimize the number of logic devices required to accommodate plural data operations during a data transfer.